发明授权
- 专利标题: Dynamically reconstructable multistage parallel single instruction multiple data array processing system
- 专利标题(中): 动态可重构多级并行单指令多数据阵列处理系统
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申请号: US14649859申请日: 2012-12-04
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公开(公告)号: US09449257B2公开(公告)日: 2016-09-20
- 发明人: Cong Shi , Nanjian Wu , Xitian Long , Jie Yang , Qi Qin
- 申请人: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
- 申请人地址: CN Beijing
- 专利权人: Institute of Semiconductors, Chinese Academy of Sciences
- 当前专利权人: Institute of Semiconductors, Chinese Academy of Sciences
- 当前专利权人地址: CN Beijing
- 代理机构: Seed IP Law Group PLLC
- 国际申请: PCT/CN2012/085814 WO 20121204
- 国际公布: WO2014/085975 WO 20140612
- 主分类号: G06K9/62
- IPC分类号: G06K9/62 ; G06F15/80 ; G06T1/20 ; G06N3/04 ; G06N3/063
摘要:
The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations. In particularly, such a system can be dynamically reconfigured as an SOM neural network at a low cost of area, and the neural network supports high level of image processing such as a high speed online neural network training and image feature recognition, and completely overcomes a defect that a high level of image processing can't be done by pixel-level parallel processing array in the existing programmable vision chips and parallel vision processors, and facilitates an intelligent and portable real time on-chip vision image system with a complete function at low device cost and low power consumption.
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