Invention Grant
- Patent Title: Layer arrangement
- Patent Title (中): 层布置
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Application No.: US14252804Application Date: 2014-04-15
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Publication No.: US09449928B2Publication Date: 2016-09-20
- Inventor: Joachim Hirschler , Gudrun Stranzl
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Viering, Jentschura & Partner mbB
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L23/00 ; H01L23/31 ; H01L23/29 ; H01L21/768 ; H01L21/308 ; H01L21/3065

Abstract:
A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.
Public/Granted literature
- US20140225233A1 LAYER ARRANGEMENT Public/Granted day:2014-08-14
Information query
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