Invention Grant
- Patent Title: Failure diagnosis circuit
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Application No.: US14695110Application Date: 2015-04-24
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Publication No.: US09455050B2Publication Date: 2016-09-27
- Inventor: Luca Molinari , Hong Wei Wang
- Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Shenzhen) R&D Co. Ltd
- Applicant Address: IT Agrate Brianza CN Shenzhen
- Assignee: STMICROELECTRONICS S.R.L.,STMICROELECTRONICS (SHENZHEN) R&D CO. LTD
- Current Assignee: STMICROELECTRONICS S.R.L.,STMICROELECTRONICS (SHENZHEN) R&D CO. LTD
- Current Assignee Address: IT Agrate Brianza CN Shenzhen
- Agency: Gardere Wynne Sewell LLP
- Priority: CN201110304946 20110927
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/18 ; G11C29/26 ; G11C29/44 ; G11C7/00 ; G11C8/00 ; G11C5/04

Abstract:
A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
Public/Granted literature
- US20150228359A1 FAILURE DIAGNOSIS CIRCUIT Public/Granted day:2015-08-13
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