Invention Grant
- Patent Title: Method and apparatus for avoiding spurs in chip
- Patent Title (中): 避免芯片杂散的方法和装置
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Application No.: US14485887Application Date: 2014-09-15
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Publication No.: US09455729B2Publication Date: 2016-09-27
- Inventor: Didier Harnay , Stephane Pineau , Francois Sittler
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Amsterdam
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Priority: EP13306263 20130916
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/107 ; H04B15/04 ; H03L7/08

Abstract:
A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.
Public/Granted literature
- US20150077165A1 METHOD AND APPARATUS FOR AVOIDING SPURS IN CHIP Public/Granted day:2015-03-19
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