A semiconductor memory device may include: a memory cell array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a page buffer block including N number of sub page buffer blocks which are arranged in a bit line direction and each of which includes a plurality of page buffers arranged in a word line direction and a bit line direction; common internal data lines respectively corresponding to the sub page buffer blocks; and a page buffer decoder including page buffer selection units which are electrically coupled between the page buffers included in each sub page buffer block and a common internal data line corresponding to the sub page buffer block and which electrically couple the page buffers included in the sub page buffer block selectively to the common internal data line.