Invention Grant
- Patent Title: Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
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Application No.: US14675156Application Date: 2015-03-31
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Publication No.: US09466720B2Publication Date: 2016-10-11
- Inventor: Qing Liu , Nicolas Loubet
- Applicant: STMICROELECTRONICS, INC.
- Applicant Address: US TX Coppell
- Assignee: STMICROELECTRONICS, INC.
- Current Assignee: STMICROELECTRONICS, INC.
- Current Assignee Address: US TX Coppell
- Agency: Seed IP Law Group PLLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L29/66 ; H01L21/762 ; H01L29/10 ; H01L29/49 ; H01L29/165 ; H01L21/02 ; H01L21/84 ; H01L27/12 ; H01L21/225 ; H01L27/092
Abstract:
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
Public/Granted literature
- US20150206972A1 METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER Public/Granted day:2015-07-23
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