A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.