发明授权
- 专利标题： Interconnect arrangement with stress-reducing structure and method of fabricating the same
- 专利标题（中）： 具有应力降低结构的互连装置及其制造方法
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申请号： US14987429申请日： 2016-01-04
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公开(公告)号： US09472508B2公开(公告)日： 2016-10-18
- 发明人: Yi-Ruei Lin , Yen-Ming Peng , Han-Wei Yang , Chen-Chung Lai
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Birch, Stewart, Kolasch & Birch, LLP
- 主分类号： H01L23/58
- IPC分类号： H01L23/58 ; H01L23/00 ; H01L23/48 ; H01L21/768 ; H01L23/31 ; H01L23/532
摘要：
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
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