Invention Grant
- Patent Title: Integrated circuit package
- Patent Title (中): 集成电路封装
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Application No.: US14205093Application Date: 2014-03-11
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Publication No.: US09472515B2Publication Date: 2016-10-18
- Inventor: Thorsten Meyer , Gerald Ofner , Teodora Ossiander , Frank Zudock , Christian Geissler
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L23/525

Abstract:
Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20150262866A1 INTEGRATED CIRCUIT PACKAGE Public/Granted day:2015-09-17
Information query
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