Invention Grant
US09472579B2 Array substrate with improved pad region 有权
阵列衬底具有改善的焊盘区域

Array substrate with improved pad region
Abstract:
An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.
Public/Granted literature
Information query
Patent Agency Ranking
0/0