Invention Grant
US09478544B2 Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device
有权
用于形成用于NMOS晶体管器件,NMOS晶体管器件和CMOS器件的锗沟道层的方法
- Patent Title: Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device
- Patent Title (中): 用于形成用于NMOS晶体管器件,NMOS晶体管器件和CMOS器件的锗沟道层的方法
-
Application No.: US14809089Application Date: 2015-07-24
-
Publication No.: US09478544B2Publication Date: 2016-10-25
- Inventor: Jerome Mitard , Roger Loo , Liesbeth Witters
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: BE Leuven
- Agency: Knobbe, Martens, Olson & Bear LLP
- Priority: EP14178468 20140725
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/02 ; H01L29/165 ; H01L29/78 ; H01L21/8238 ; H01L29/04

Abstract:
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.
Public/Granted literature
Information query
IPC分类: