Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.