The present disclosure provides an array substrate, including a plurality of sub-pixel regions arranged in a matrix form. Each sub-pixel region may at least include a first thin film transistor (TFT) and a second thin film transistor. The first thin film transistor may include a first gate electrode, a first source electrode and a first drain electrode. The second thin film transistor may include a second gate electrode, a second source electrode and a second drain electrode. The first gate electrode and at least one of the second source electrode and the second drain electrode may be provided on a same layer. The second gate electrode and at least one of the first source electrode and the first drain electrode may be provided on a same layer. The second gate electrode and the first source electrode may be integrated together.