Invention Grant
US09488996B2 Bias techniques and circuit arrangements to reduce leakage current in a circuit
有权
偏置技术和电路布置，以减少电路中的漏电流
- Patent Title: Bias techniques and circuit arrangements to reduce leakage current in a circuit
- Patent Title (中): 偏置技术和电路布置，以减少电路中的漏电流
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Application No.: US14691461Application Date: 2015-04-20
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Publication No.: US09488996B2Publication Date: 2016-11-08
- Inventor: Frederic Bossu , Ahmed Abdel Monem Youssef , Tsai-Pi Hung , Prasad Srinivasa Siva Gudem
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: G05F1/46
- IPC: G05F1/46 ; H02H9/04 ; H01L27/02
Abstract:
An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.
Public/Granted literature
- US20150346743A1 BIAS TECHNIQUES AND CIRCUIT ARRANGEMENTS TO REDUCE LEAKAGE CURRENT IN A CIRCUIT Public/Granted day:2015-12-03
Information query
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