A detecting circuit comprises a first to a third detecting line, a first and a second control line, and a first to a sixth transistor set. Each transistor set comprises a first and a second transistor, a control terminal thereof couples to the first and the second control line, respectively, a first terminal thereof couples to one of the first to the third detecting line, a second terminal thereof couples to the second terminal of the second transistor in the same transistor set. The connection nodes compose a dot set [(3,3), (2,2), (3,1), (2,3), (3,2), (2,1)], wherein the numerals 1-3 represent the first to the third detecting line, a first and a second numeral of a dot represent that a first terminal of the first and the second transistor connect to the detecting lines represented by the numerals, respectively.