Invention Grant
- Patent Title: Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device
- Patent Title (中): 包括ESD保护器件,ESD保护电路,集成电路和制造半导体器件的方法的半导体器件
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Application No.: US14419064Application Date: 2012-08-22
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Publication No.: US09490243B2Publication Date: 2016-11-08
- Inventor: Jean Philippe Laine , Patrice Besse
- Applicant: Jean Philippe Laine , Patrice Besse
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/IB2012/001774 WO 20120822
- International Announcement: WO2014/030026 WO 20140227
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/8222 ; H01L27/06 ; H01L29/06 ; H01L29/10

Abstract:
A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.
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