Invention Grant
US09494649B2 Adaptive digital delay line for characterization of clock uncertainties
有权
用于表征时钟不确定度的自适应数字延迟线
- Patent Title: Adaptive digital delay line for characterization of clock uncertainties
- Patent Title (中): 用于表征时钟不确定度的自适应数字延迟线
-
Application No.: US13731583Application Date: 2012-12-31
-
Publication No.: US09494649B2Publication Date: 2016-11-15
- Inventor: Arun S. Iyer , Prashanth Vallur , Shraddha Padiyar , Amit Govil
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: H03K5/14
- IPC: H03K5/14 ; G01R31/317 ; H03K5/1534 ; H03K5/13

Abstract:
An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
Public/Granted literature
- US20140184243A1 ADAPTIVE DIGITAL DELAY LINE FOR CHARACTERIZATION OF CLOCK UNCERTAINTIES Public/Granted day:2014-07-03
Information query
IPC分类: