发明授权
US09496369B2 Method of forming split-gate memory cell array along with low and high voltage logic devices
有权
与低压和高压逻辑器件一起形成分离栅极存储单元阵列的方法
- 专利标题: Method of forming split-gate memory cell array along with low and high voltage logic devices
- 专利标题(中): 与低压和高压逻辑器件一起形成分离栅极存储单元阵列的方法
-
申请号: US15002307申请日: 2016-01-20
-
公开(公告)号: US09496369B2公开(公告)日: 2016-11-15
- 发明人: Man-Tang Wu , Jeng-Wei Yang , Chien-Sheng Su , Chun-Ming Chen , Nhan Do
- 申请人: Silicon Storage Technology, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Silicon Storage Technology, Inc.
- 当前专利权人: Silicon Storage Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: DLA Piper LLP (US)
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L29/66 ; H01L29/423 ; H01L27/115
摘要:
A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.
公开/授权文献
信息查询
IPC分类: