发明授权
US09496369B2 Method of forming split-gate memory cell array along with low and high voltage logic devices 有权
与低压和高压逻辑器件一起形成分离栅极存储单元阵列的方法

Method of forming split-gate memory cell array along with low and high voltage logic devices
摘要:
A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.
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