Invention Grant
- Patent Title: Process for integrated circuit fabrication including a uniform depth tungsten recess technique
- Patent Title (中): 集成电路制造工艺，包括均匀的深度钨凹陷技术
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Application No.: US14512700Application Date: 2014-10-13
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Publication No.: US09502302B2Publication Date: 2016-11-22
- Inventor: Qing Liu , Ruilong Xie , Chun-Chen Yeh
- Applicant: STMicroelectronics, Inc. , GlobalFoundries Inc , International Business Machines Corporation
- Applicant Address: US TX Coppell KY Grand Cayman US NY Armonk
- Assignee: STMicroelectronics, Inc.,GlobalFoundries Inc,International Business Machines Corporation
- Current Assignee: STMicroelectronics, Inc.,GlobalFoundries Inc,International Business Machines Corporation
- Current Assignee Address: US TX Coppell KY Grand Cayman US NY Armonk
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/423
Abstract:
Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.
Public/Granted literature
- US20160104644A1 PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE Public/Granted day:2016-04-14
Information query
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