Invention Grant
US09507089B2 Method of manufacturing a photonic integrated circuit optically coupled to a laser of III-V material
有权
制造与III-V材料激光光学耦合的光子集成电路的方法
- Patent Title: Method of manufacturing a photonic integrated circuit optically coupled to a laser of III-V material
- Patent Title (中): 制造与III-V材料激光光学耦合的光子集成电路的方法
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Application No.: US14804629Application Date: 2015-07-21
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Publication No.: US09507089B2Publication Date: 2016-11-29
- Inventor: Alain Chantre , Sébastien Cremer
- Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Montrouge FR Crolles
- Assignee: STMICROELECTRONICS SA,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: STMICROELECTRONICS SA,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Montrouge FR Crolles
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: FR1457861 20140818
- Main IPC: G02B6/12
- IPC: G02B6/12 ; G02B6/10 ; C03B37/022 ; H01L21/00 ; H01L31/102 ; G02B6/136 ; H01S5/343 ; H01S5/026 ; H01S5/02 ; G02B6/132 ; G02B6/42

Abstract:
A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.
Public/Granted literature
- US20160047986A1 METHOD OF MANUFACTURING A PHOTONIC INTEGRATED CIRCUIT OPTICALLY COUPLED TO A LASER OF III-V MATERIAL Public/Granted day:2016-02-18
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