A thin film transistor substrate, includes: pixels disposed in a display area of the thin film transistor substrate and connected to gate lines and data lines; gate pad parts connected to first ends of the gate lines; first test transistors each being connected to a second end of a corresponding gate line of the gate lines; data pad parts connected to first ends of the data lines; and second test transistors each being connected to a second end of a corresponding data line of the data lines. The gate pad parts, the data pad parts, the first test transistors, and the second test transistors are disposed in a non-display area of the thin film transistor substrate. The first test transistors are configured to be switched to receive a first inspection signal and the second test transistors are configured to be switched to receive a second inspection signal.