发明授权
US09524264B2 Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media
有权
使用共享总线系统中的异步主设备参考时钟以及相关方法,设备和计算机可读介质来生成组合总线时钟信号
- 专利标题: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media
- 专利标题(中): 使用共享总线系统中的异步主设备参考时钟以及相关方法,设备和计算机可读介质来生成组合总线时钟信号
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申请号: US14316026申请日: 2014-06-26
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公开(公告)号: US09524264B2公开(公告)日: 2016-12-20
- 发明人: Yossi Amon , David Asher Friedman , Ben Levin , Sharon Graif
- 申请人: QUALCOMM Incorporated
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 代理机构: Withrow & Terranova, PLLC
- 主分类号: G06F13/36
- IPC分类号: G06F13/36 ; G06F13/42 ; G06F13/364
摘要:
Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.
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