Invention Grant
US09530503B2 And-type SGVC architecture for 3D NAND flash 有权
用于3D NAND闪存的And-SGVC架构

And-type SGVC architecture for 3D NAND flash
Abstract:
A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.
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