Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.