Invention Grant
- Patent Title: Interconnection of multiple chips in a package
- Patent Title (中): 封装中多个芯片的互连
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Application No.: US13996107Application Date: 2011-12-22
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Publication No.: US09535865B2Publication Date: 2017-01-03
- Inventor: Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
- Applicant: Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/066976 WO 20111222
- International Announcement: WO2013/095538 WO 20130627
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/364 ; G06F13/14 ; G06F13/40 ; G06F13/42 ; G06F3/0488 ; G06F13/16
Abstract:
An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
Public/Granted literature
- US20140201405A1 INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES Public/Granted day:2014-07-17
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