发明授权
- 专利标题： Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional interconnection, and metal film-forming composition for three-dimensional interconnection
- 专利标题（中）： 用于形成三维互连的方法，包括三维互连的电路装置和用于三维互连的金属成膜组合物
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申请号： US14836236申请日： 2015-08-26
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公开(公告)号： US09543201B2公开(公告)日： 2017-01-10
- 发明人: Kenzou Ookita , Isao Aritome , Keisuke Kuriyama , Taichi Matsumoto , Kazuto Watanabe , Atsushi Kobayashi , Sugirou Shimoda
- 申请人： JSR Corporation
- 申请人地址： JP Minato-ku
- 专利权人： JSR Corporation
- 当前专利权人： JSR Corporation
- 当前专利权人地址： JP Minato-ku
- 代理机构： Oblon, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2014-173318 20140827; JP2014-173343 20140827
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L23/535 ; H01L23/522 ; H01L23/485 ; H01L23/498 ; H01L21/48 ; H01L21/288 ; H01L23/48 ; H01L23/14 ; H01L23/532
摘要：
In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process.
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