Semiconductor device and method of manufacturing semiconductor device

Invention Grant

US09543217B2 Semiconductor device and method of manufacturing semiconductor device 有权

Title translation: 半导体装置及其制造方法

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Patent Title: Semiconductor device and method of manufacturing semiconductor device
Patent Title (中): 半导体装置及其制造方法
Application No.: US15150516

Application Date: 2016-05-10
Publication No.: US09543217B2

Publication Date: 2017-01-10
Inventor: Yoshiaki Toyoda , Hideaki Katakura , Takatoshi Ooe
Applicant: FUJI ELECTRIC CO., LTD.
Applicant Address: JP Kawasaki-shi, Kanagawa
Assignee: FUJI ELECTRIC CO., LTD.
Current Assignee: FUJI ELECTRIC CO., LTD.
Current Assignee Address: JP Kawasaki-shi, Kanagawa
Agency: Rabin & Berdo, P.C.
Priority: JP2014-100389 20140514
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/265

Semiconductor device and method of manufacturing semiconductor device

Abstract:

One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract(Chinese):

一个实施例包括用于输出级的垂直n沟道功率MOSFET和用于控制垂直n沟道功率MOSFET的水平p沟道MOSFET设置在单个半导体衬底上。水平p沟道MOSFET具有在栅电极处以自对准方式形成的Psd（一p +型源区和一p +型漏区）。 Psd具有设置在其中的p +型扩散区域，使得Psd部分地具有高杂质浓度。 p +型扩散区域通过与垂直n沟道功率MOSFET的p +型扩散区域同时离子注入形成的并且具有比常规接触孔窄的宽度的接触孔连接到相应的金属布线层。以这种方式，可以在金属布线层和半导体部分之间改善接触性能，并且可以实现尺寸减小。

Public/Granted literature

US20160254198A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2016-09-01

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS