Invention Grant
- Patent Title: Vertical junction FinFET device and method for manufacture
- Patent Title (中): 垂直结FinFET器件及其制造方法
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Application No.: US14677404Application Date: 2015-04-02
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Publication No.: US09543304B2Publication Date: 2017-01-10
- Inventor: Qing Liu , John Hongguang Zhang
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/085 ; H01L27/098 ; H01L29/78 ; H01L29/808 ; H01L29/417 ; H01L29/10 ; H01L21/283

Abstract:
A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.
Public/Granted literature
- US20160293602A1 VERTICAL JUNCTION FINFET DEVICE AND METHOD FOR MANUFACTURE Public/Granted day:2016-10-06
Information query
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