Invention Grant
- Patent Title: High speed complementary NMOS LUT logic
- Patent Title (中): 高速互补NMOS LUT逻辑
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Application No.: US14611069Application Date: 2015-01-30
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Publication No.: US09543950B2Publication Date: 2017-01-10
- Inventor: Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
- Applicant: Lattice Semiconductor Corporation
- Applicant Address: US OR Portland
- Assignee: LATTICE SEMICONDUCTOR CORPORATION
- Current Assignee: LATTICE SEMICONDUCTOR CORPORATION
- Current Assignee Address: US OR Portland
- Main IPC: H03K19/00
- IPC: H03K19/00 ; H03K19/177 ; H03K19/0948

Abstract:
A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.
Public/Granted literature
- US20160020767A1 HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC Public/Granted day:2016-01-21
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