Invention Grant
US09548289B2 Semiconductor package assemblies with system-on-chip (SOC) packages
有权
具有片上系统(SOC)封装的半导体封装组件
- Patent Title: Semiconductor package assemblies with system-on-chip (SOC) packages
- Patent Title (中): 具有片上系统(SOC)封装的半导体封装组件
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Application No.: US14741796Application Date: 2015-06-17
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Publication No.: US09548289B2Publication Date: 2017-01-17
- Inventor: Tzu-Hung Lin , Ming-Tzong Yang
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/34 ; H01L25/18 ; H01L25/065 ; H01L25/10 ; H01L23/31 ; H01L23/50 ; H01L23/00 ; H05K1/11 ; H05K1/18

Abstract:
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.
Public/Granted literature
- US20160079220A1 SEMICONDUCTOR PACKAGE ASSEMBLY Public/Granted day:2016-03-17
Information query
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