A thin film transistor array panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction; a data line extending in a different second direction; a first common signal distribution line including a plurality of first branches connected to each other, wherein the first branches extend in the second direction and intersect under or over with the first gate line and the second gate line. The first branches are connected to receive an electrostatic offset voltage of polarity opposite to that of data line voltages supplied on the data line. A column of pixel-electrodes are sandwiched between the data line and one of the first branches.