Invention Grant
US09548722B2 Apparatus and methods for reducing glitches in digital step attenuators
有权
用于减少数字步进衰减器中的毛刺的装置和方法
- Patent Title: Apparatus and methods for reducing glitches in digital step attenuators
- Patent Title (中): 用于减少数字步进衰减器中的毛刺的装置和方法
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Application No.: US14719241Application Date: 2015-05-21
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Publication No.: US09548722B2Publication Date: 2017-01-17
- Inventor: Yusuf Alperen Atesal , Peter J. Katzin
- Applicant: Analog Devices Global
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Global
- Current Assignee: Analog Devices Global
- Current Assignee Address: BM Hamilton
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H03H11/24
- IPC: H03H11/24 ; H03H7/25

Abstract:
Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.
Public/Granted literature
- US20160118959A1 APPARATUS AND METHODS FOR REDUCING GLITCHES IN DIGITAL STEP ATTENUATORS Public/Granted day:2016-04-28
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