Invention Grant
US09552244B2 Real time correction of bit failure in resistive memory 有权
电阻存储器中位故障的实时校正

Real time correction of bit failure in resistive memory
Abstract:
Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.
Public/Granted literature
Information query
Patent Agency Ranking
0/0