An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the transmitter that synchronize transmission of data with a clock signal while in a first mode, (b) save the transmit parameters in response to a command received while in the first mode, and (c) transmit additional data while in a second mode using the transmit parameters learned while in the first mode. The circuit may have a receiver in communication with the memory. The circuit may be configured to (a) train receive parameters of the receiver that synchronize reception of the data with the clock signal while the memory is in the first mode and (b) receive the additional data from the memory while the memory is in the second mode using the receive parameters learned while the memory was in the first mode.