Invention Grant
- Patent Title: Semiconductor structure with TRL and handle wafer cavities
- Patent Title (中): 具有TRL和处理晶圆腔的半导体结构
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Application No.: US14633024Application Date: 2015-02-26
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Publication No.: US09553013B2Publication Date: 2017-01-24
- Inventor: Michael A. Stuber , George Imthurn
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/762 ; H01L21/84 ; H01L21/02 ; H01L21/20 ; H01L21/768 ; H01L21/302 ; H01L23/48 ; H01L29/78 ; H01L27/12 ; B81C1/00
Abstract:
A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.
Public/Granted literature
- US20150179505A1 SEMICONDUCTOR STRUCTURE WITH TRL AND HANDLE WAFER CAVITIES Public/Granted day:2015-06-25
Information query
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