Metrology may be implemented during semiconductor device fabrication by a) modeling a first measurement on a first test cell formed in a layer of a partially fabricated device; b) performing a second measurement on a second test cell in the layer; c) feeding information from the second measurement into the modeling of the first measurement; and after a lithography pattern has been formed on the layer including the first and second test cells, d) modeling a third and a fourth measurement on the first and second test cells respectively using information from a) and b) respectively.