Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.