Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.