Invention Grant
US09569296B2 Receiver bit alignment for multi-lane asynchronous high-speed data interface 有权
多通道异步高速数据接口的接收器位对齐

Receiver bit alignment for multi-lane asynchronous high-speed data interface
Abstract:
The invention uses a PRBS pattern generated by transmitter (serializer) as training. At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple lanes simultaneously. The captured data is used to calculate the PRBS distance for different lanes. After the distances are obtained, the one with largest latency is used as a reference, to calculate the relative latency with each other lane. This relative latency is further used to calculate the number of shifts for Barrel Shifter and word shifter.
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