Invention Grant
- Patent Title: Receiver bit alignment for multi-lane asynchronous high-speed data interface
- Patent Title (中): 多通道异步高速数据接口的接收器位对齐
-
Application No.: US14293570Application Date: 2014-06-02
-
Publication No.: US09569296B2Publication Date: 2017-02-14
- Inventor: Junqiang Hu , Ting Wang , Sadaichiro Ogushi
- Applicant: NEC Laboratories America, Inc.
- Applicant Address: JP Tokyo
- Assignee: NEC CORPORATION
- Current Assignee: NEC CORPORATION
- Current Assignee Address: JP Tokyo
- Agent Joseph Kolodka
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F7/58

Abstract:
The invention uses a PRBS pattern generated by transmitter (serializer) as training. At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple lanes simultaneously. The captured data is used to calculate the PRBS distance for different lanes. After the distances are obtained, the one with largest latency is used as a reference, to calculate the relative latency with each other lane. This relative latency is further used to calculate the number of shifts for Barrel Shifter and word shifter.
Public/Granted literature
- US20140365835A1 Receiver Bit Alignment for Multi-Lane Asynchronous High-Speed Data Interface Public/Granted day:2014-12-11
Information query