Invention Grant
- Patent Title: Semiconductor package assembly with through silicon via interconnect
- Patent Title (中): 半导体封装组件通过硅芯片通过互连
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Application No.: US14963451Application Date: 2015-12-09
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Publication No.: US09570399B2Publication Date: 2017-02-14
- Inventor: Ming-Tzong Yang , Cheng-Chou Hung , Wei-Che Huang , Yu-Hua Huang , Tzu-Hung Lin , Kuei-Ti Chan , Ruey-Beei Wu , Kai-Bin Wu
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsin-Chu
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L23/48 ; H01L21/768 ; H01L23/498 ; H01L23/00

Abstract:
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
Public/Granted literature
- US20160181201A1 SEMICONDUCTOR PACKAGE ASSEMBLY WITH THROUGH SILICON VIA INTERCONNECT Public/Granted day:2016-06-23
Information query
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