Invention Grant
- Patent Title: Multi-stage interconnect network in a parallel processing network device
- Patent Title (中): 并行处理网络设备中的多级互联网络
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Application No.: US14482980Application Date: 2014-09-10
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Publication No.: US09571380B2Publication Date: 2017-02-14
- Inventor: Aviran Kadosh , Rami Zemach
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H04L12/26
- IPC: H04L12/26 ; H04L12/715 ; H04L12/803 ; H04L12/933 ; H04L12/931

Abstract:
A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.
Public/Granted literature
- US20150071079A1 MULTI-STAGE INTERCONNECT NETWORK IN A PARALLEL PROCESSING NETWORK DEVICE Public/Granted day:2015-03-12
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