发明授权
US09576814B2 Method of spacer patterning to form a target integrated circuit pattern
有权
间隔物图案化以形成目标集成电路图案的方法
- 专利标题： Method of spacer patterning to form a target integrated circuit pattern
- 专利标题（中）： 间隔物图案化以形成目标集成电路图案的方法
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申请号： US14853857申请日： 2015-09-14
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公开(公告)号： US09576814B2公开(公告)日： 2017-02-21
- 发明人: Chieh-Han Wu , Cheng-Hsiung Tsai , Chung-Ju Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L21/308
- IPC分类号： H01L21/308 ; H01L21/02 ; H01L21/033 ; H01L21/027 ; H01L21/306 ; H01L21/311 ; H01L21/768
摘要：
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
公开/授权文献
- US20160005617A1 METHOD FOR INTEGRATED CIRCUIT PATTERNING 公开/授权日：2016-01-07
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