发明授权
US09576875B2 Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
有权
用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
- 专利标题： Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
- 专利标题（中）： 用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
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申请号： US14591014申请日： 2015-01-07
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公开(公告)号： US09576875B2公开(公告)日： 2017-02-21
- 发明人: Reinhard Hess , Katharina Umminger , Gabriel Maier , Markus Menath , Gunther Mackh , Hannes Eder , Alexander Heinrich
- 申请人： Infineon Technologies AG
- 申请人地址： DE Neubiberg
- 专利权人： INFINEON TECHNOLOGIES AG
- 当前专利权人： INFINEON TECHNOLOGIES AG
- 当前专利权人地址： DE Neubiberg
- 代理机构： Viering, Jentschura & Partner mbB
- 主分类号： H01L23/31
- IPC分类号： H01L23/31 ; H01L23/485 ; H01L21/78 ; H01L21/3065 ; H01L21/56 ; H01L23/00 ; H01L21/683 ; H01L21/02 ; H01L21/768
摘要：
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
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