A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.