Invention Grant
- Patent Title: Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition
- Patent Title (中): 具有控制单元的多核处理器，其响应于同步条件向所有核产生中断请求
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Application No.: US14281681Application Date: 2014-05-19
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Publication No.: US09588572B2Publication Date: 2017-03-07
- Inventor: G. Glenn Henry , Terry Parks
- Applicant: VIA TECHNOLOGIES, INC.
- Applicant Address: TW New Taipei
- Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee Address: TW New Taipei
- Agent E. Alan Davis; James W. Huffman
- Main IPC: G06F13/32
- IPC: G06F13/32 ; G06F1/00 ; G06F1/32 ; G06F12/08 ; G06F13/24 ; G06F9/44 ; G06F13/364 ; G06F9/38 ; G06F9/30 ; G06F1/04 ; G06F1/12
Abstract:
A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.
Public/Granted literature
- US20150067215A1 MULTI-CORE SYNCHRONIZATION MECHANISM WITH INTERRUPTS ON SYNC CONDITION Public/Granted day:2015-03-05
Information query
