发明授权
- 专利标题: Memory controller and decoding method
- 专利标题(中): 内存控制器和解码方式
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申请号: US14743061申请日: 2015-06-18
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公开(公告)号: US09588772B2公开(公告)日: 2017-03-07
- 发明人: Daiki Watanabe , Daisuke Fujiwara , Ryo Yamaki
- 申请人: Kabushiki Kaisha Toshiba
- 申请人地址: JP Minato-ku
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Minato-ku
- 代理机构: Oblon, McClelland, Maier & Neustadt, L.L.P.
- 主分类号: H03M13/03
- IPC分类号: H03M13/03 ; G06F9/30
摘要:
According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.
公开/授权文献
- US20160246603A1 MEMORY CONTROLLER AND DECODING METHOD 公开/授权日:2016-08-25
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