Invention Grant
- Patent Title: Store cache for transactional memory
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Application No.: US14537131Application Date: 2014-11-10
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Publication No.: US09588893B2Publication Date: 2017-03-07
- Inventor: Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Isaac J. Gooshaw
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F3/06

Abstract:
A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.
Public/Granted literature
- US20160132434A1 STORE CACHE FOR TRANSACTIONAL MEMORY Public/Granted day:2016-05-12
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