A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors.