A static RAM having a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, of which potential is higher than a reference potential, and a drive line; a column switch having transistor pairs which connect one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of writing of the memory cell, where a well of the transistor pairs of the column switch is connected to the drive line.